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MOTOROLA
Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc.
Order Number: MPC9446/D Rev 1, 03/2002
2.5V and 3.3V LVCMOS Clock Fanout Buffer
The MPC9446 is a 2.5V and 3.3V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3V, 2.5V and dual supply voltages are supported for mixed-voltage applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9446 is specified for the extended temperature range of --40C to 85C. Features * Configurable 10 outputs LVCMOS clock distribution buffer
MPC9446
LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5V AND 3.3V LVCMOS CLOCK DISTRIBUTION BUFFER
Freescale Semiconductor, Inc...
* Compatible to single, dual and mixed 3.3V/2.5V voltage supply * Wide range output clock frequency up to 250 MHz * Designed for mid-range to high-performance telecom, networking and
computer applications
* * * * * *
Supports applications requiring clock redundancy Max. output skew of 200 ps (150 ps within one bank) Selectable output configurations per output bank Tristable outputs 32 ld LQFP package
FA SUFFIX LQFP PACKAGE CASE 873A
Ambient operating temperature range of --40 to 85C Functional Description The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs.
All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package.
(c) Motorola, Inc. 2002
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MPC9446
Freescale Semiconductor, Inc.
VCC 25k VCC 25k
Bank A
0 1
CCLK0 CCLK1 CCLK_SEL
CLK CLK / 2
0 1
QA0 QA1 QA2
25k
0 1
Bank B
QB0 QB1 QB2 QC0 QC1 QC2 QC3
FSELA
25k 25k 25k 25k
0 1
Bank C
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FSELB FSELC MR/OE
Figure 1. MPC9446 Logic Diagram
VCCC
VCCB
VCCB
GND
GND
QB0
QB1
QB2
VCCB is internally connected to VCC 24 VCCA QA2 GND QA1 VCCA QA0 GND MR/OE 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 QC3 GND QC2 VCCC QC1 GND QC0 VCCC
MPC9446
13 12 11 10 9
CCLK_SEL
CCLK0
CCLK1
VCC
FSELC
FSELA
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
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FSELB
GND
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Table 1: Pin Configuration
Pin CCLK0,1 FSELA, FSELB, FSELC MR/OE GND VCCA, VCCB*, VCCC VCC QA0 - QA2 QB0 - QB2 QC0 - QC3 Output Output Output Input Input Input I/O Type LVCMOS LVCMOS LVCMOS Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS clock inputs Output bank divide select input Internal reset and output (high impedance) control Negative voltage supply (GND) Positive voltage supply for output banks Positive voltage supply for core (VCC) Bank A outputs Bank B outputs Bank C outputs Function
MPC9446
* VCCB is internally connected to VCC.
Table 2: Supported Single and Dual Supply Configurations
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Supply voltage configuration 3.3V Mixed voltage supply 2.5V a. b. c. d.
VCCa 3.3V 3.3V 2.5V
VCCAb 3.3V 3.3V or 2.5V 2.5V
VCCBc 3.3V 3.3V 2.5V
VCCCd 3.3V 3.3V or 2.5V 2.5V
GND 0V 0V 0V
VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels Control Default 0 0 0 0 0 CCLK0 fQA0:2 = fREF fQB0:2 = fREF fQC0:3 = fREF Outputs enabled 0 CCLK1 fQA0:2 = fREF / 2 fQB0:2 = fREF / 2 fQC0:3 = fREF / 2 Internal reset Outputs disabled (tristate) 1
Table 3: Function Table (Controls)
CCLK_SEL FSELA FSELB FSELC MR/OE
Table 4: Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
Table 5: General Specifications
Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Condition
TIMING SOLUTIONS
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MPC9446
Freescale Semiconductor, Inc.
Table 6: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V 5%, TA = --40C to +85C)
Symbol VIH VIL IIN VOH VOL ZOUT ICCQc Characteristics Input High Voltage Input Low Voltage Input Currenta Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current 14 - 17 2.0 2.4 0.55 0.30 Min 2.0 -0.3 Typ Max VCC + 0.3 0.8 200 Unit V V A V V V mA All VCC Pins Condition LVCMOS LVCMOS VIN=GND or VIN=VCC IOH=-24 mAb IOL= 24mAb IOL= 12mA
a. Input pull-up / pull-down resistors influence input current. b. The MPC9446 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
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Table 7: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V 5%, TA = --40C to +85C)a
Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) Characteristics Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-device Skew Output pulse skewd /1 output /2 output 47 45 0.1 50 50 CCLK0,1 to any Q CCLK0,1 to any Q 2.2 2.2 2.8 2.8 /1 output /2 output Min 0 0 0 1.4 1.0c 4.45 4.2 10 10 150 200 350 2.25 200 53 55 1.0 Typ Max 250b 250b 125 Unit MHz MHz MHz ns ns ns ns ns ns ps ps ps ns ps % % ns DCREF = 50% DCREF = 25%-75% 0.55 to 2.4V 0.8 to 2.0V FSELx=0 FSELx=1 Condition
tsk(PP) tSK(P) DCQ tr, tf
Output Duty Cycle Output Rise/Fall Time
a. AC characteristics apply for parallal output termination of 50 to VTT. b. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. d. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
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TIMING SOLUTIONS
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Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V 5%, TA = --40C to +85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICCQc Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb Maximum Quiescent Supply Current 17 - 20b 200 2.0 Min 1.7 -0.3 1.8 0.6 Typ Max VCC + 0.3 0.7 Unit V V V V A mA
MPC9446
Condition LVCMOS LVCMOS IOH=-15 mAa IOL= 15 mA VIN=GND or VIN=VCC All VCC Pins
a. The MPC9446 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. b. Input pull-up / pull-down resistors influence input current. c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
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Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V 5%, TA = --40C to +85C)a b
Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-device Skew Output pulse skewe Output Duty Cycle Output Rise/Fall Time /1 or /2 output 45 0.1 50 CCLK0,1 to any Q CCLK0,1 to any Q 2.6 2.6 /1 output /2 output Characteristics Min 0 0 0 1.4 1.0d 5.6 5.5 10 10 150 200 350 3.0 200 55 1.0 Typ Max 250c 250b 125 Unit MHz MHz MHz ns ns ns ns ns ns ps ps ps ns ps % ns DCREF = 50% 0.6 to 1.8V 0.7 to 1.7V FSELx=0 FSELx=1 Condition
tsk(PP) tSK(P) DCQ tr, tf a. b. c. d.
AC characteristics apply for parallel output termination of 50 to VTT. AC specifications are design targets, final specification is pending device characterization. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. e. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%, TA = --40C to +85C)a b
Symbol tsk(O) Characteristics Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-device Skew Propagation delay Output pulse skewc Output Duty Cycle /1 or /2 output 45 50 CCLK0,1 to any Q See 3.3V table 250 55 ps % DCREF = 50% Min Typ Max 150 250 350 2.5 Unit ps ps ps ns Condition
tsk(PP) tPLH,HL tSK(P) DCQ
a. AC characteristics apply for parallel output termination of 50 to VTT. b. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank. c. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
TIMING SOLUTIONS
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MPC9446
Freescale Semiconductor, Inc.
APPLICATIONS INFORMATION
Driving Transmission Lines The MPC9446 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9446 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9446 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9446 OUTPUT BUFFER IN
14
impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: = VS ( Z0 / (RS+R0 +Z0)) = 50 || 50 = 36 || 36 = 14 = 3.0 ( 25 / (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 2.5 2.0 In 1.5 1.0 0.5 OutA tD = 3.8956 OutB tD = 3.9386
VL Z0 RS R0 VL
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RS = 36
ZO = 50 OutA
VOLTAGE (V)
0 2 4 6 8 TIME (nS) 10 12 14
MPC9446 OUTPUT BUFFER IN
14
Figure 4. Single versus Dual Waveforms
RS = 36 ZO = 50 OutB0 ZO = 50 OutB1
RS = 36
Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9446 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9446. The output waveform in Figure 4. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9446 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 5. Optimized Dual Line Termination
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TIMING SOLUTIONS
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MPC9446 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
MPC9446
RT = 50 VTT
RT = 50 VTT
Figure 6. CCLK0,1 MPC9446 AC test reference for Vcc = 3.3V and Vcc = 2.5V
VCC=3.3V 2.4
VCC=2.5V 1.8V 0.6V
CCLK
VCC VCC/2 GND VCC VCC/2 GND t(LH) t(HL)
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0.55 tF tR
QX
Figure 7. Output Transition Time Test Reference
Figure 8. Propagation delay (tPD) test reference
VCC VCC/2 GND QX t(LH) t(HL) VCC VCC/2 GND
VCC VCC/2 GND VCC VCC/2 GND tSK(LH) tSK(HL)
CCLK
The pin-- to-- pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device
tSK(P) = | tPLH - tPHL |
Figure 9. Output- -output Skew tSK(LH, HL) -to-
Figure 10. Output Pulse Skew (tSK(P)) test reference
VCC VCC/2 GND tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage TN TN+1 TJIT(CC) = |TN - TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
Figure 11. Output Duty Cycle (DC)
Figure 12. Cycle- -cycle Jitter -to-
TIMING SOLUTIONS
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MPC9446
Freescale Semiconductor, Inc.
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A
25 4X
32
A1
0.20 (0.008) AB T-- U Z
1
- TB B1
8
- UV DETAIL Y
17
AE P
V1 AE DETAIL Y 0.20 (0.008) AC T-- U Z
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE - AB-- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS - T-- , - U-- , AND - Z-- TO BE DETERMINED AT DATUM PLANE - AB-- . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE - AC-- . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE - AB-- . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
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9
9
- ZS1 S
4X
G - ABSEATING PLANE
DETAIL AD
- ACBASE METAL
N F
8X
M_
R
J
0.20 (0.008)
D
M
AC T-- U Z
0.10 (0.004) AC
CE
SECTION AE- AE -
DETAIL AD
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GAUGE PLANE
X
0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
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TIMING SOLUTIONS
- T- , - U- , - Z-
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NOTES
MPC9446
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MPC9446
Freescale Semiconductor, Inc.
NOTES
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TIMING SOLUTIONS
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NOTES
MPC9446
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MPC9446
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